In speculative Tomasulo, the ReOrderBuffer (ROB), contains the instruction before the result of an instruction is updated in the register file. So, In oder to exist any hazard, the hazard should be in the ROB.
WAW Hazard:
Assume,
Instruction i : R1 = R1 + R2
Instruction i+1 : R1 = R3- R4.
Now, even though, if (i+1) instruction is finished earlier before ith instruction, they are kept in the ROB first before they are commited. Now, the commit becomes in order ( first ith instruction and then (i+1) th instruction ). So, it does not matter which instruction first updated the ROB entry. This is the way, WAW hazard is removed.
WAR:
Assume,
ith instruction: R1 = R2 + R3
(i+1)th instruction: R2 = R5 + R6
In order to avoid WAR hazard, R2 must be read first by Instruction i before (i+1) instruction overwrite it.
It happens in Tomasulo, because, instruction is issued in Order and when an instruction is issued, the reservation station tracks down how it can get its operand from. So, As i is issued first, R2 will always be read before i+1 overwrite it.
RAW: If there is a dependency on a register which is not yet completed, the reservation station keeps tract of which other Reservation station is going to produce it. So, it does not make RAW Hazard.
RAR: Not a hazard anyway in Speculative tomasulo.
